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EDIGIM Research
Private Limited
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Responsible for configurable IP verification process flow development and track to ensure on time delivery and bug free design through reusable test bench, firmware verification early in the design, process automation and formal verification.
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Experience in developing testbench, bfmand uvc’s using system Verilog and UVM methodologies for data path and control path related designs.
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Experience in creating test plan, functional coverage plan for block level and soc level verification and closure though coding testcases, writing checkers, functional coverage and code coverage measurement.
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Experience on simulation and debugging tools like Cadence Ncsim, IFV, simvision and Synopsys VCS, Verdi.
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Experience on formal verification using SVA, PSL with VC Formal and Cadence IFV.
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Experience in DPI based firmware API and ARM M0 based boot code functional verification.
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Worked on Ethernet MAC standard IEEE 802.3, L2/L3 layers and serdes based design core verifications.
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Experience in SOC protocols like AXI, APB, CAN and JDEC DDR3/DDR4 Memory interface standards.
ATPG for stuck-at and at-speed fault models using Synopsys
Developed the test setup procedure to program the SoC to scanmode
ATPG DRC analysis/fixing and TDF coverage improvement
Serial and parallel patterns validation using VCS simulator.
Expertise in place & route for block build/full chip development with timing closure using industry standard tools for tasks like Synthesis, Floor Plan, Placement, CTS, Signal Integrity, IR Draw, EM, Low Power Checks and Signoff checks. Extensive Knowledge in physical verification like DRC, LVS, Antenna, Density in latest nodes like 14nm, 10nm. Experience in DFT Techniques like Scan, Bist, ATPG, Boundary Scan.
Expertise in Layout of analog components like ADC, DAC, PLL, Bandgap, Power regulators etc. Experience in designing standard cell libraries that meet several design criteria like optimal area, power, timing etc. on several technology nodes. Specialists in high speed high density memories and associated modules. In depth understanding of design of IO cells and interfaces having unique electrical and noise specifications.
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